Convolution IP core


The Convolution filter core accelerates computation of the image convolution filter. It allows real-time (60+fps) Full-HD processing on Xilinx 7-series devices.


The core contains multiple computation modules in the core:

  • 5×5 convolution module with 1024p support, RAW/RGB pixel format, user controllable computation precision
  • Coloring module
  • Format conversion module
  • DMA mode

The core is AMBA AXI4 compilant, fully validated under Xilinx EDK/Vivado*.

See leaflet for brief information or download datasheet for more details.

Soon we will add ZedBoard based demo desing.

If you are interested in the IP core licensing or if you require more information, please contact us.

Project (TG01010117/PROSYKO) was supported by the TA CR.